The present disclosure relates to hardware development tools. More particularly, the present disclosure relates to digital circuit testing and emulation systems.
The simulation time of a conventional simulation system generally increases exponentially with an increasing circuit size. If there is an error during a functional verification, an additional simulation needs to be made from the beginning of the simulation to a time after the error position. The error position is typically detected by searching backwards from the primary port in the top level.
If the states are known for all of the storage units in a target digital circuit, a distributed simulation can be made in terms of time and space. The ability to quickly save, restore and change the states of the storage units is important in Distributed Simultaneous-Cycle Based Simulation (DS-CBS), for example.
As shown in FIG. 1, a conventional digital circuit testing system is indicated generally by the reference numeral 100. The system 100 includes original logic 110 and additional logic 120. Here, the original logic 110 includes a first flip-flop 112 combinational logic 114 in signal communication with the first flip-flop 112, and a second flip-flop 116 in signal communication with the combinational logic 114. The additional logic 120 includes control logic 122, a multiplexer 124 in signal communication with the control logic 122 and the first flip-flop 112, a third flip-flop 126 in signal communication with the multiplexer 124, and a memory 128 in signal communication with the third flip-flop 126.
In the conventional digital circuit testing system 100, the additional logic 120 is used to save the states of the storage units. The additional control logic, flip-flops and memory are used to monitor the states of the original flip-flops and nets. For example, the additional flip-flop F3 or 126 is assigned to save the state of the original flip-flop F1 or 112. A Normal clock, Nclk and a sampling clock, Dclk, are provided. States of the storage units of the original logic are sampled and saved to the fixed capacity embedded memory 128, and the data in the memory is output with a Joint Test Action Group (JTAG) interface.
Unfortunately, the storage capacity has a fixed limit because of the size of the embedded memory 128. Because Nclk and Dclk are always running, it is impossible to monitor the original logic in real time. The memory outputs the previous states of the running logic. In addition, no feedback path is provided to restore the stored states to the original logic.
Turning to FIG. 2, another conventional digital circuit testing system is indicated generally by the reference numeral 200. The system 200 includes original logic 210 and additional logic 230. The original logic includes a first flip-flop 212, an inverter 214 in signal communication with the first flip-flop, a first NAND gate 216 in signal communication with the inverter, a second NAND gate 218 in signal communication with the first NAND gate, a second flip-flop 220 in signal communication with the second NAND gate, a third NAND gate 222 in signal communication with the second flip-flop, and a third flip-flap 224 in signal communication with the third NAND gate.
The additional logic 230 includes a first multiplexer 232 in signal communication with the first flip-flop 212, a fourth flip-flap 234 in signal communication with the first multiplexer, a second multiplexer 236 in signal communication with the second flip-flop 220 and the fourth flip-flop, a fifth flip-flap 238 in signal communication with the second multiplexer, and a third multiplexer 240 in signal communication with the fifth flip-flop.
The conventional system 200 has no embedded memory, but does have the additional control logic and flip-flops to monitor the states of original flip-flops and nets. The system 200 uses register shifting to save the captured states of the additional logic in order to monitor the original logic. That is, the additional logic is used to monitor or test the original logic. Unfortunately, the system 200 also lacks a feedback path to restore the captured states to the original logic.
Turning now to FIG. 3, yet another conventional digital circuit testing system is indicated generally by the reference numeral 300. Here, a first model 310 includes a sequential circuit 312 in signal communication with flip-flops 314, 316 (not shown) and 318. A second model 340 includes the sequential circuit 312 in signal communication with the flip-flops 314, 316 and 318, and a scan circuit 350.
The scan circuit 350 includes a scan_enable terminal 368; a scan_in terminal 352; a first multiplexer 354 in signal communication with the scan_enable terminal, the combinational circuit 312, and the scan_in terminal; the first flip-flop 314 in signal communication with the first multiplexer; a second multiplexer 358 in signal communication with the scan_enable terminal, the combinational circuit 312, and the first flip-flop; the second flip-flop 316 in signal communication with the second multiplexer; a third multiplexer 362 in signal communication with the scan_enable terminal, the combinational circuit 312, and the second flip-flop; the third flip-flop 318 in signal communication with the third multiplexer; and a scan_out terminal 366 in signal communication with the third flip-flop.
Unfortunately, the system 300 uses the scan chain or circuit 350 only to test the original logic. A real scan flip-flop is used in a scan chain to capture and shift the states of the original logic. New test bench data is serially input during serial outputting of the captured data. In addition, no feedback path is provided to restore the captured states to the original logic during serial outputting of the captured data.
Thus, various conventional systems may require an extra hardware flip-flop to measure an existing flip-flop, cannot monitor in realtime, have no feedback loop, and/or are only suited for testing rather than for emulation. The present disclosure addresses these and other issues.